![]() BCD CounterĬreate a 4-bit decimal (BCD) counter that continuously counts 0-9. Connect the 1Hz output to an LED and verify it flashes at 1Hz. Create a second clock divider that produces a 1Hz output clock from a 1KHz input clock. Counter Based Clock DividerĬreate a counter/clock divider to produce a 1KHz output clock from a 100MHz input clock. ![]() Configure your Blackboard, and verify the LEDS toggle at the correct rate. Connect the 4-bit counter outputs to four LEDs. 5Hz to use as a clock for the 4-bit counter. Select a bit from the 28-bit counter that toggles at about. Design a clock divider based on a synchronous binary counterĭefine a 28-bit synchronous binary counter that uses the 100MHz clock, and a second 4-bit counter that uses one of the bits from the 28-bit counter as a clock. The counter uses the main Blackboard 100Mhz clock as an input, and it should generate a clock signal below 1Hz to drive the LED (hint: see the Asynch Divider topic document) 2. Design a clock divider based on an asynchronous counterĬreate a clock divider that uses a structural asynchronous counter built from Xilinx flip-flop primitives. The resulting circuit is a purely combinational circuit (the code could have been written linearly, without using a for loop, but it would have been much longer).Requirements 1. Note the for loop does not directly describe a circuit – rather, it describes how the circuit components that will do the required shifting and adding are to be assembled. ![]() Here, a for loop is used to make the code more compact. Verilog code to implement the double-dabble is shown below. An illustration of the double-dabble algorithm The figure below illustrates the process (the blue boxes around BCD digits show BCD digits that are >=5, and therefore need 3 to be added). Adding three to any BCD digit greater than five does two things: first, at the next shift, the 3 that was added becomes 6, and that accounts for the difference in binary and BCD codes (BCD uses 10 binary codes, and binary uses 16) and second, adding 3 forces the MSB of the BCD digit to a 1, where it is “carried out” and into the next digit. Since BCD digits cannot exceed nine, a pre-shift number of five or more would result in a post-shift number of ten or more, which cannot be represented. This works because every left shift multiplies all BCD digits by two. After every shift, all BCD digits are examined, and 3 is added to any BCD digit that is currently 5 or greater. The binary number is left-shifted once for each of its bits, with bits shifted out of the MSB of the binary number and into the LSB of the accumulating BCD number. The “double dabble” algorithm is commonly used to convert a binary number to BCD. The Verilog code below illustrates converting a 4-digit BCD number to it’s binary equivalent. To find the binary equivalent, each BCD digit is multiplied by its weighted magnitude: 9 x 10^2 + 8 * 10^1 + 7 * 10^0, or 9 * 100 + 8 * 10+ 7 * 1. Consider the BCD number 987, stored as three 4-bit BCD codes: 1001 for 9 (digit 2), 1000 for 8 (digit 1), and 0111 for 7 (digit 0). Each BCD digit in a given number contributes a magnitude equal to the digit multiplied by its weight, and each digit’s weight is equal to 10 raised to the power of the digit’s position in the number. BCD numbers are representations of decimal (base 10) numbers, and like all modern number systems, BCD numbers use positional weighting.
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